
sqrt:     file format elf64-littleaarch64


Disassembly of section .init:

0000000000400518 <_init>:
  400518:	a9bf7bfd 	stp	x29, x30, [sp, #-16]!
  40051c:	910003fd 	mov	x29, sp
  400520:	94000036 	bl	4005f8 <call_weak_fn>
  400524:	a8c17bfd 	ldp	x29, x30, [sp], #16
  400528:	d65f03c0 	ret

Disassembly of section .plt:

0000000000400530 <.plt>:
  400530:	a9bf7bf0 	stp	x16, x30, [sp, #-16]!
  400534:	90000090 	adrp	x16, 410000 <__FRAME_END__+0xf658>
  400538:	f947fe11 	ldr	x17, [x16, #4088]
  40053c:	913fe210 	add	x16, x16, #0xff8
  400540:	d61f0220 	br	x17
  400544:	d503201f 	nop
  400548:	d503201f 	nop
  40054c:	d503201f 	nop

0000000000400550 <sqrt@plt>:
  400550:	b0000090 	adrp	x16, 411000 <sqrt@GLIBC_2.17>
  400554:	f9400211 	ldr	x17, [x16]
  400558:	91000210 	add	x16, x16, #0x0
  40055c:	d61f0220 	br	x17

0000000000400560 <__libc_start_main@plt>:
  400560:	b0000090 	adrp	x16, 411000 <sqrt@GLIBC_2.17>
  400564:	f9400611 	ldr	x17, [x16, #8]
  400568:	91002210 	add	x16, x16, #0x8
  40056c:	d61f0220 	br	x17

0000000000400570 <rand@plt>:
  400570:	b0000090 	adrp	x16, 411000 <sqrt@GLIBC_2.17>
  400574:	f9400a11 	ldr	x17, [x16, #16]
  400578:	91004210 	add	x16, x16, #0x10
  40057c:	d61f0220 	br	x17

0000000000400580 <__gmon_start__@plt>:
  400580:	b0000090 	adrp	x16, 411000 <sqrt@GLIBC_2.17>
  400584:	f9400e11 	ldr	x17, [x16, #24]
  400588:	91006210 	add	x16, x16, #0x18
  40058c:	d61f0220 	br	x17

0000000000400590 <abort@plt>:
  400590:	b0000090 	adrp	x16, 411000 <sqrt@GLIBC_2.17>
  400594:	f9401211 	ldr	x17, [x16, #32]
  400598:	91008210 	add	x16, x16, #0x20
  40059c:	d61f0220 	br	x17

00000000004005a0 <printf@plt>:
  4005a0:	b0000090 	adrp	x16, 411000 <sqrt@GLIBC_2.17>
  4005a4:	f9401611 	ldr	x17, [x16, #40]
  4005a8:	9100a210 	add	x16, x16, #0x28
  4005ac:	d61f0220 	br	x17

Disassembly of section .text:

00000000004005b0 <_start>:
  4005b0:	d280001d 	mov	x29, #0x0                   	// #0
  4005b4:	d280001e 	mov	x30, #0x0                   	// #0
  4005b8:	aa0003e5 	mov	x5, x0
  4005bc:	f94003e1 	ldr	x1, [sp]
  4005c0:	910023e2 	add	x2, sp, #0x8
  4005c4:	910003e6 	mov	x6, sp
  4005c8:	580000c0 	ldr	x0, 4005e0 <_start+0x30>
  4005cc:	580000e3 	ldr	x3, 4005e8 <_start+0x38>
  4005d0:	58000104 	ldr	x4, 4005f0 <_start+0x40>
  4005d4:	97ffffe3 	bl	400560 <__libc_start_main@plt>
  4005d8:	97ffffee 	bl	400590 <abort@plt>
  4005dc:	00000000 	.inst	0x00000000 ; undefined
  4005e0:	00400838 	.word	0x00400838
  4005e4:	00000000 	.word	0x00000000
  4005e8:	004008c8 	.word	0x004008c8
  4005ec:	00000000 	.word	0x00000000
  4005f0:	00400948 	.word	0x00400948
  4005f4:	00000000 	.word	0x00000000

00000000004005f8 <call_weak_fn>:
  4005f8:	90000080 	adrp	x0, 410000 <__FRAME_END__+0xf658>
  4005fc:	f947f000 	ldr	x0, [x0, #4064]
  400600:	b4000040 	cbz	x0, 400608 <call_weak_fn+0x10>
  400604:	17ffffdf 	b	400580 <__gmon_start__@plt>
  400608:	d65f03c0 	ret
  40060c:	00000000 	.inst	0x00000000 ; undefined

0000000000400610 <deregister_tm_clones>:
  400610:	b0000080 	adrp	x0, 411000 <sqrt@GLIBC_2.17>
  400614:	91010000 	add	x0, x0, #0x40
  400618:	b0000081 	adrp	x1, 411000 <sqrt@GLIBC_2.17>
  40061c:	91010021 	add	x1, x1, #0x40
  400620:	eb00003f 	cmp	x1, x0
  400624:	540000a0 	b.eq	400638 <deregister_tm_clones+0x28>  // b.none
  400628:	90000001 	adrp	x1, 400000 <_init-0x518>
  40062c:	f944b421 	ldr	x1, [x1, #2408]
  400630:	b4000041 	cbz	x1, 400638 <deregister_tm_clones+0x28>
  400634:	d61f0020 	br	x1
  400638:	d65f03c0 	ret
  40063c:	d503201f 	nop

0000000000400640 <register_tm_clones>:
  400640:	b0000080 	adrp	x0, 411000 <sqrt@GLIBC_2.17>
  400644:	91010000 	add	x0, x0, #0x40
  400648:	b0000081 	adrp	x1, 411000 <sqrt@GLIBC_2.17>
  40064c:	91010021 	add	x1, x1, #0x40
  400650:	cb000021 	sub	x1, x1, x0
  400654:	9343fc21 	asr	x1, x1, #3
  400658:	8b41fc21 	add	x1, x1, x1, lsr #63
  40065c:	9341fc21 	asr	x1, x1, #1
  400660:	b40000a1 	cbz	x1, 400674 <register_tm_clones+0x34>
  400664:	90000002 	adrp	x2, 400000 <_init-0x518>
  400668:	f944b842 	ldr	x2, [x2, #2416]
  40066c:	b4000042 	cbz	x2, 400674 <register_tm_clones+0x34>
  400670:	d61f0040 	br	x2
  400674:	d65f03c0 	ret

0000000000400678 <__do_global_dtors_aux>:
  400678:	a9be7bfd 	stp	x29, x30, [sp, #-32]!
  40067c:	910003fd 	mov	x29, sp
  400680:	f9000bf3 	str	x19, [sp, #16]
  400684:	b0000093 	adrp	x19, 411000 <sqrt@GLIBC_2.17>
  400688:	39410260 	ldrb	w0, [x19, #64]
  40068c:	35000080 	cbnz	w0, 40069c <__do_global_dtors_aux+0x24>
  400690:	97ffffe0 	bl	400610 <deregister_tm_clones>
  400694:	52800020 	mov	w0, #0x1                   	// #1
  400698:	39010260 	strb	w0, [x19, #64]
  40069c:	f9400bf3 	ldr	x19, [sp, #16]
  4006a0:	a8c27bfd 	ldp	x29, x30, [sp], #32
  4006a4:	d65f03c0 	ret

00000000004006a8 <frame_dummy>:
  4006a8:	17ffffe6 	b	400640 <register_tm_clones>

00000000004006ac <havesamenum>:
  4006ac:	d100c3ff 	sub	sp, sp, #0x30
  4006b0:	b9000fe0 	str	w0, [sp, #12]
  4006b4:	b9002fff 	str	wzr, [sp, #44]
  4006b8:	f9000fff 	str	xzr, [sp, #24]
  4006bc:	790043ff 	strh	wzr, [sp, #32]
  4006c0:	14000020 	b	400740 <havesamenum+0x94>
  4006c4:	b9400fe1 	ldr	w1, [sp, #12]
  4006c8:	528ccce0 	mov	w0, #0x6667                	// #26215
  4006cc:	72acccc0 	movk	w0, #0x6666, lsl #16
  4006d0:	9b207c20 	smull	x0, w1, w0
  4006d4:	d360fc00 	lsr	x0, x0, #32
  4006d8:	13027c02 	asr	w2, w0, #2
  4006dc:	131f7c20 	asr	w0, w1, #31
  4006e0:	4b000042 	sub	w2, w2, w0
  4006e4:	2a0203e0 	mov	w0, w2
  4006e8:	531e7400 	lsl	w0, w0, #2
  4006ec:	0b020000 	add	w0, w0, w2
  4006f0:	531f7800 	lsl	w0, w0, #1
  4006f4:	4b000020 	sub	w0, w1, w0
  4006f8:	b9002be0 	str	w0, [sp, #40]
  4006fc:	b9802be0 	ldrsw	x0, [sp, #40]
  400700:	910063e1 	add	x1, sp, #0x18
  400704:	38606820 	ldrb	w0, [x1, x0]
  400708:	11000400 	add	w0, w0, #0x1
  40070c:	12001c02 	and	w2, w0, #0xff
  400710:	b9802be0 	ldrsw	x0, [sp, #40]
  400714:	910063e1 	add	x1, sp, #0x18
  400718:	38206822 	strb	w2, [x1, x0]
  40071c:	b9400fe0 	ldr	w0, [sp, #12]
  400720:	528ccce1 	mov	w1, #0x6667                	// #26215
  400724:	72acccc1 	movk	w1, #0x6666, lsl #16
  400728:	9b217c01 	smull	x1, w0, w1
  40072c:	d360fc21 	lsr	x1, x1, #32
  400730:	13027c21 	asr	w1, w1, #2
  400734:	131f7c00 	asr	w0, w0, #31
  400738:	4b000020 	sub	w0, w1, w0
  40073c:	b9000fe0 	str	w0, [sp, #12]
  400740:	b9400fe0 	ldr	w0, [sp, #12]
  400744:	7100001f 	cmp	w0, #0x0
  400748:	54fffbec 	b.gt	4006c4 <havesamenum+0x18>
  40074c:	14000004 	b	40075c <havesamenum+0xb0>
  400750:	b9402fe0 	ldr	w0, [sp, #44]
  400754:	11000400 	add	w0, w0, #0x1
  400758:	b9002fe0 	str	w0, [sp, #44]
  40075c:	b9802fe0 	ldrsw	x0, [sp, #44]
  400760:	910063e1 	add	x1, sp, #0x18
  400764:	38606820 	ldrb	w0, [x1, x0]
  400768:	7100041f 	cmp	w0, #0x1
  40076c:	54000088 	b.hi	40077c <havesamenum+0xd0>  // b.pmore
  400770:	b9402fe0 	ldr	w0, [sp, #44]
  400774:	7100241f 	cmp	w0, #0x9
  400778:	54fffecd 	b.le	400750 <havesamenum+0xa4>
  40077c:	b9402fe0 	ldr	w0, [sp, #44]
  400780:	7100241f 	cmp	w0, #0x9
  400784:	5400006c 	b.gt	400790 <havesamenum+0xe4>
  400788:	52800020 	mov	w0, #0x1                   	// #1
  40078c:	14000002 	b	400794 <havesamenum+0xe8>
  400790:	52800000 	mov	w0, #0x0                   	// #0
  400794:	9100c3ff 	add	sp, sp, #0x30
  400798:	d65f03c0 	ret

000000000040079c <test_sqrt>:
  40079c:	a9bf7bfd 	stp	x29, x30, [sp, #-16]!
  4007a0:	910003fd 	mov	x29, sp
  4007a4:	90000000 	adrp	x0, 400000 <_init-0x518>
  4007a8:	9125e000 	add	x0, x0, #0x978
  4007ac:	1e601000 	fmov	d0, #2.000000000000000000e+00
  4007b0:	97ffff7c 	bl	4005a0 <printf@plt>
  4007b4:	d503201f 	nop
  4007b8:	a8c17bfd 	ldp	x29, x30, [sp], #16
  4007bc:	d65f03c0 	ret

00000000004007c0 <rand_sqrt>:
  4007c0:	a9be7bfd 	stp	x29, x30, [sp, #-32]!
  4007c4:	910003fd 	mov	x29, sp
  4007c8:	97ffff6a 	bl	400570 <rand@plt>
  4007cc:	2a0003e1 	mov	w1, w0
  4007d0:	5290a3e0 	mov	w0, #0x851f                	// #34079
  4007d4:	72aa3d60 	movk	w0, #0x51eb, lsl #16
  4007d8:	9b207c20 	smull	x0, w1, w0
  4007dc:	d360fc00 	lsr	x0, x0, #32
  4007e0:	13057c02 	asr	w2, w0, #5
  4007e4:	131f7c20 	asr	w0, w1, #31
  4007e8:	4b000040 	sub	w0, w2, w0
  4007ec:	52800c82 	mov	w2, #0x64                  	// #100
  4007f0:	1b027c00 	mul	w0, w0, w2
  4007f4:	4b000020 	sub	w0, w1, w0
  4007f8:	1e620000 	scvtf	d0, w0
  4007fc:	fd000fa0 	str	d0, [x29, #24]
  400800:	90000000 	adrp	x0, 400000 <_init-0x518>
  400804:	91262000 	add	x0, x0, #0x988
  400808:	fd400fa0 	ldr	d0, [x29, #24]
  40080c:	97ffff65 	bl	4005a0 <printf@plt>
  400810:	fd400fa0 	ldr	d0, [x29, #24]
  400814:	97ffff4f 	bl	400550 <sqrt@plt>
  400818:	fd000ba0 	str	d0, [x29, #16]
  40081c:	90000000 	adrp	x0, 400000 <_init-0x518>
  400820:	91262000 	add	x0, x0, #0x988
  400824:	fd400ba0 	ldr	d0, [x29, #16]
  400828:	97ffff5e 	bl	4005a0 <printf@plt>
  40082c:	d503201f 	nop
  400830:	a8c27bfd 	ldp	x29, x30, [sp], #32
  400834:	d65f03c0 	ret

0000000000400838 <main>:
  400838:	a9be7bfd 	stp	x29, x30, [sp, #-32]!
  40083c:	910003fd 	mov	x29, sp
  400840:	97ffffd7 	bl	40079c <test_sqrt>
  400844:	97ffffdf 	bl	4007c0 <rand_sqrt>
  400848:	52802780 	mov	w0, #0x13c                 	// #316
  40084c:	b9001ba0 	str	w0, [x29, #24]
  400850:	90000000 	adrp	x0, 400000 <_init-0x518>
  400854:	91264000 	add	x0, x0, #0x990
  400858:	b9401ba1 	ldr	w1, [x29, #24]
  40085c:	97ffff51 	bl	4005a0 <printf@plt>
  400860:	52800020 	mov	w0, #0x1                   	// #1
  400864:	b9001fa0 	str	w0, [x29, #28]
  400868:	14000010 	b	4008a8 <main+0x70>
  40086c:	b9401fa1 	ldr	w1, [x29, #28]
  400870:	b9401fa0 	ldr	w0, [x29, #28]
  400874:	1b007c20 	mul	w0, w1, w0
  400878:	b90017a0 	str	w0, [x29, #20]
  40087c:	b94017a0 	ldr	w0, [x29, #20]
  400880:	97ffff8b 	bl	4006ac <havesamenum>
  400884:	7100041f 	cmp	w0, #0x1
  400888:	540000a1 	b.ne	40089c <main+0x64>  // b.any
  40088c:	90000000 	adrp	x0, 400000 <_init-0x518>
  400890:	91268000 	add	x0, x0, #0x9a0
  400894:	b94017a1 	ldr	w1, [x29, #20]
  400898:	97ffff42 	bl	4005a0 <printf@plt>
  40089c:	b9401fa0 	ldr	w0, [x29, #28]
  4008a0:	11000400 	add	w0, w0, #0x1
  4008a4:	b9001fa0 	str	w0, [x29, #28]
  4008a8:	b9401fa1 	ldr	w1, [x29, #28]
  4008ac:	b9401ba0 	ldr	w0, [x29, #24]
  4008b0:	6b00003f 	cmp	w1, w0
  4008b4:	54fffdcb 	b.lt	40086c <main+0x34>  // b.tstop
  4008b8:	d503201f 	nop
  4008bc:	a8c27bfd 	ldp	x29, x30, [sp], #32
  4008c0:	d65f03c0 	ret
  4008c4:	00000000 	.inst	0x00000000 ; undefined

00000000004008c8 <__libc_csu_init>:
  4008c8:	a9bc7bfd 	stp	x29, x30, [sp, #-64]!
  4008cc:	910003fd 	mov	x29, sp
  4008d0:	a901d7f4 	stp	x20, x21, [sp, #24]
  4008d4:	90000094 	adrp	x20, 410000 <__FRAME_END__+0xf658>
  4008d8:	90000095 	adrp	x21, 410000 <__FRAME_END__+0xf658>
  4008dc:	91374294 	add	x20, x20, #0xdd0
  4008e0:	913722b5 	add	x21, x21, #0xdc8
  4008e4:	a902dff6 	stp	x22, x23, [sp, #40]
  4008e8:	cb150294 	sub	x20, x20, x21
  4008ec:	f9001ff8 	str	x24, [sp, #56]
  4008f0:	2a0003f6 	mov	w22, w0
  4008f4:	aa0103f7 	mov	x23, x1
  4008f8:	9343fe94 	asr	x20, x20, #3
  4008fc:	aa0203f8 	mov	x24, x2
  400900:	97ffff06 	bl	400518 <_init>
  400904:	b4000194 	cbz	x20, 400934 <__libc_csu_init+0x6c>
  400908:	f9000bb3 	str	x19, [x29, #16]
  40090c:	d2800013 	mov	x19, #0x0                   	// #0
  400910:	f8737aa3 	ldr	x3, [x21, x19, lsl #3]
  400914:	aa1803e2 	mov	x2, x24
  400918:	aa1703e1 	mov	x1, x23
  40091c:	2a1603e0 	mov	w0, w22
  400920:	91000673 	add	x19, x19, #0x1
  400924:	d63f0060 	blr	x3
  400928:	eb13029f 	cmp	x20, x19
  40092c:	54ffff21 	b.ne	400910 <__libc_csu_init+0x48>  // b.any
  400930:	f9400bb3 	ldr	x19, [x29, #16]
  400934:	a941d7f4 	ldp	x20, x21, [sp, #24]
  400938:	a942dff6 	ldp	x22, x23, [sp, #40]
  40093c:	f9401ff8 	ldr	x24, [sp, #56]
  400940:	a8c47bfd 	ldp	x29, x30, [sp], #64
  400944:	d65f03c0 	ret

0000000000400948 <__libc_csu_fini>:
  400948:	d65f03c0 	ret

Disassembly of section .fini:

000000000040094c <_fini>:
  40094c:	a9bf7bfd 	stp	x29, x30, [sp, #-16]!
  400950:	910003fd 	mov	x29, sp
  400954:	a8c17bfd 	ldp	x29, x30, [sp], #16
  400958:	d65f03c0 	ret
